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cy2dl1504 1:4 differential lvds fanout buffer with selectable clock input cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-56312 rev. *f revised march 29, 2011 features select between low-voltage positive emitter-coupled logic (lvpecl) or low-voltage differential signal (lvds) input pairs to distribute to four lvds output pairs 30-ps maximum output-to-output skew 480-ps maximum propagation delay 0.11-ps maximum additive rms phase jitter at 156.25 mhz (12-khz to 20-mhz offset) up to 1.5-ghz operation output enable and synchronous clock enable functions 20-pin thin shrunk small outline package (tssop) 2.5-v or 3.3-v operating voltage [1] commercial and industrial operating temperature range functional description the cy2dl1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differ ential lvds fanout buffer targeted to meet the requirements of high-speed clock distribution applications. the cy2dl1504 can select between lvpecl or lvds input clock pair s using the in_sel pin. the synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. the output enable function allows the outputs to be asynchronously driven to a high-impedance state. the device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 ghz. note 1. input ac-coupling capacitors are required for voltage-translation applications. logic block diagram q0 q0# q1 q1# q2 q2# q3 q3# in0 in0# in1 in1# r p in_sel v dd v ss clk_en r p v dd d q oe r p v dd [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 2 of 14 contents pinout ................................................................................ 3 absolute maximum ratings ............................................ 4 operating conditions....................................................... 4 dc electrical specifications ............................................ 5 ac electrical specifications ............................................ 6 ordering information........................................................ 9 ordering code definition............................................. 9 package diagram............................................................ 10 acronyms ........................................................................ 11 document conventions ................................................. 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 14 worldwide sales and design supp ort............. .......... 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 3 of 14 pinout figure 1. pin diagram ? cy2dl1504 20-pin tssop package 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 cy2dl1504 q0 q0# v dd q1 q1# q2 q2# v ss q3 q3# v ss clk_en in_sel in0 in0# in1 in1# oe v ss v dd table 1. pin definitions pin no. pin name pin type description 1,9,13 v ss power ground 2 clk_en input synchronous clock enable. low-voltage complementary metal oxide semiconductor (lvcmos)/low-voltage tr ansistor-transistor-logic (lvttl); when clk_en = low, q(0:3) outputs are held low and q(0:3)# outputs are held high 3 in_sel input input clock select pin. lvcmos/lvttl; when in_sel = low, the in0/in0# differential input pair is active when in_sel = high, the in1/in1# differential input pair is active 4 in0 input lvds input clock. active when in_sel = low 5 in0# input lvds complementary input clock. active when in_sel = low 6 in1 input lvpecl input clock. active when in_sel = high 7 in1# input lvpecl complementary input clock. active when in_sel = high 8 oe input output enable. lvcmos/lvttl; when oe = low, q(0:3) and q(0:3)# outputs are disabled (see i oz ) 10,18 v dd power power supply 11,14,16,19 q(0:3)# output lvds complementary output clocks 12,15,17,20 q(0:3) output lvds output clocks [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 4 of 14 absolute maximum ratings parameter description condition min max unit v dd supply voltage nonfunctional ?0.5 4.6 v v in [2] input voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v v out [2] dc output or i/o voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v t s storage temperature nonfunctional ?55 150 c esd hbm electrostatic discharge (esd) protection (human body model) jedec std 22-a114-b 2000 ? v l u latch up meets or exceeds jedec spec jesd78b ic latch up test ul?94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 3 operating conditions parameter description condition min max unit v dd supply voltage 2.5-v supply 2.375 2.625 v 3.3-v supply 3.135 3.465 v t a ambient operating temperature commercial 0 70 c industrial ?40 85 c t pu power ramp time power-up time for v dd to reach minimum specified voltage. (power ramp must be monotonic) 0.05 500 ms note 2. the voltage on any i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 5 of 14 dc electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min max unit i dd operating supply current all lvds outputs terminated with a load of 100 [3, 4] ?61ma v ih1 input high voltage, lvds and lvpecl input clocks, in0, in0#, in1, and in1# ?v dd + 0.3 v v il1 input low voltage, lvds and lvpecl input clocks, in0, in0#, in1, and in1# ?0.3 ? v v ih2 input high voltage, clk_en, in_sel, and oe v dd = 3.3 v 2.0 v dd + 0.3 v v il2 input low voltage, clk_en, in_sel, and oe v dd = 3.3 v ?0.3 0.8 v v ih3 input high voltage, clk_en, in_sel, and oe v dd = 2.5 v 1.7 v dd + 0.3 v v il3 input low voltage, clk_en, in_sel, and oe v dd = 2.5 v ?0.3 0.7 v v id_lvds [5] lvds input differential amplitude see figure 3 on page 7 0.4 0.8 v v id_lvpecl [5] lvpecl input differential amplitude see figure 3 on page 7 0.4 1.0 v v icm input common mode voltage see figure 3 on page 7 0.5 v dd ? 0.2 v i ih input high current, all inputs input = v dd [6] ?150 a i il input low current, all inputs input = v ss [6] ?150 ? a v pp lvds differential output voltage peak to peak, single-ended v dd = 3.3 v or 2.5 v, r term = 100 between q and q# pairs [3, 7] 250 470 mv v ocm lvds differential output common mode voltage v dd = 3.3 v or 2.5 v, r term = 100 between q and q# pairs [3, 7] 1.125 1.375 v v ocm change in v ocm between complementary output states v dd = 3.3 v or 2.5 v, r term = 100 between q and q# pairs [3, 7] ?50mv i oz output leakage current oe = v ss, v out = 0.75v ? 1.75v ?15 15 a r p internal pull-up/pull-down resistance, lvcmos logic inputs clk_en has pull-up only in_sel has pull-down only oe has pull-up only 60 165 k c in input capacitance measured at 10 mhz; per pin ? 3 pf notes 3. refer to figure 2 on page 7. 4. i dd includes current that is dissipated externally in the output termination resistors. 5. v id minimum of 400 mv is required to meet all output ac el ectrical specifications. the device is functional with v id minimum of greater than 200 mv. 6. positive current flows into the input pin, negative current flows out of the input pin. 7. refer to figure 4 on page 7. [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 6 of 14 ac electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min typ max unit f in input frequency dc ? 1.5 ghz f out output frequency f out = f in dc ? 1.5 ghz t pd [8] propagation delay input pair to output pair input rise/fall time < 1.5 ns (20% to 80%) ??480ps t odc [9] output duty cycle diff input at 50% duty cycle frequency range up to 1 ghz 48?52% t sk1 [10] output-to-output skew any ou tput to any output, with same load conditions at dut ??30ps t sk1 d [10] device-to-device output skew any output to any output between two or more devices. devices must have the same input and have the same output load. ??150ps pn add additive rms phase noise 156.25 mhz input rise/fall time < 150 ps (20% to 80%) v id > 400 mv offset = 1 khz ? ? ?120 dbc/hz offset = 10 khz ? ? ?135 dbc/hz offset = 100 khz ? ? ?135 dbc/hz offset = 1 mhz ? ? ?150 dbc/hz offset = 10 mhz ? ? ?154 dbc/hz offset = 20 mhz ? ? ?155 dbc/hz t jit [11] additive rms phase jitter (random) 156.25 mhz, 12 khz to 20 mhz offset; input rise/fall time < 150 ps (20% to 80%), v id > 400 mv ??0.11ps t r , t f [12] output rise/fall ti me, single-ended 50% duty cycle at input, 20% to 80% of full swing (v ol to v oh ) input rise/fall time < 1.5 ns (20% to 80%) measured at 1 ghz. ??300ps t sod time from clock edge to outputs disabled synchronous clock enable (clk_en) switched low ??700ps t soe time from clock edge to outputs enabled synchronous clock enable (clk_en) switched high ??700ps notes 8. refer to figure 5 on page 7. 9. refer to figure 6 on page 7. 10. refer to figure 7 on page 8. 11. refer to figure 8 on page 8. 12. refer to figure 9 on page 8. [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 7 of 14 figure 2. lvds output termination figure 3. input differential and common mode voltages figure 4. output differential and common mode voltages figure 5. input to any output pair propagation delay figure 6. output duty cycle q# z=50 100 buf q z=50 in v a v b in# v icm = (v a + v b )/2 v id q v a v b q# v ocm = (v a + v b )/2 v pp v ocm = | v ocm1 ? v ocm2 | in# in t pd q x # q x t pw t odc = t pw t period t period q x # q x [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 8 of 14 figure 7. output-to-outpu t and device-to -device skew figure 8. rms phase jitter figure 9. output rise/fall time figure 10. synchronous clock enable timing q x # q x q y # q y q z # q z t sk1 t sk1 d device 1 device 2 phase noise phase noise mark offset frequency f1 f2 a rea under the masked phase noise plot noise powe r rms jitter [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 9 of 14 ordering information ordering code definition part number type production flow pb-free cy2dl1504zxc 20-pin tssop commercial, 0 c to 70 c cy2dl1504zxct 20-pin tssop commercial, 0 c to 70 c cy2dl1504zxi 20-pin tssop industrial, ?40 c to 85 c cy2dl1504zxit 20-pin tssop industrial, ?40 c to 85 c cy base part number 2dl15 04 number of differential output pairs company id: cy = cypress zx pb-free tssop package temperature range c = commercial i = industrial c/i t tape and reel [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 10 of 14 package diagram figure 11. 20-pin thin shrunk small outline package (4.40 mm body) zz20 51-85118 *c [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 11 of 14 acronyms document conventions table 2. acronyms used in this document acronym description esd electrostatic discharge hbm human body model jedec joint electron devices engineering council lvds low-voltage differential signal lvcmos low-voltage complementary metal oxide semiconductor lvpecl low-voltage positive emitter-coupled logic lvttl low-voltage transistor-transistor logic oe output enable rms root mean square tssop thin shrunk small outline package table 3. units of measure symbol unit of measure c degree celsius dbc decibels relati ve to the carrier ghz giga hertz hz hertz k kilo ohm a micro amperes f micro farad s micro second ma milliamperes ms millisecond mv millivolt mhz megahertz ns nano second ohm pf pico farad ps pico second vvolts wwatts [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 12 of 14 document history page document title: cy2dl1504 1:4 differential lvds fanout buffer with selectable clock input document number: 001-56312 revision ecn orig. of change submission date description of change ** 2782891 cxq 10/09/09 new datasheet. *a 2838613 cxq 01/05/2010 changed status fr om ?advance? to ?preliminary?. changed from 0.34 ps to 0.25 ps maximum additive jitter in ?features? on page 1 and in t jit in the ac electrical specs table on page 5. added t pu spec to the operating conditions table on page 3. changed max i dd spec in the dc electrical specs table on page 4 from 60 ma to 61 ma. removed v od and v od specs from the dc electrical specs table on page 4. changed i oz in the dc electrical specs table on page 4 from min of -10 ua to -15 ua and from max of 10 ua to 15 ua. added r p spec in the dc electrical specs table on page 4. min = 60 k , max = 140 k . added a measurement definition for c in in the dc electrical specs table on page 4. added v pp and v pp specs to the ac electrical specs table on page 5. v pp min = 250 mv and max = 470 mv; v pp max = 50 mv. changed letter case and some names of all the timing parameters in the ac electrical specs table on page 5 to be consistent with eros. lowered all additive phase noise mask specs by 3 db in the ac electrical specs table on page 5. added condition to t r and t f specs in the ac electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). changed letter case and some names of all the timing parameters in figures 4, 5, 6, 7 and 9, to be c onsistent with eros. updated figure 4 with definition for v pp and v pp . *b 3010332 cxq 08/18/2010 changed from 0.25 ps to 0.11 ps maximum additive jitter in ?features? on page 1 and in t jit in the ac electrical specs table on page 5. added ?functional equivalent to ics8543i? to the ?features? section. changed pin 13 in figure 1 and table 1 from v dd to v ss . changed pin 8 description in table 1 from ?high impedance? to ?disabled?. added note 6 to describe i ih and i il specs. removed reference to data distribution from ?functional description?. changed r p for diff inputs from 100 k to 150 k in the logic block diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the dc electrical specs table. split v id into separate specs in dc electrical specs table: 0.4 v min and 0.8 v max for lvds, 0.4 v mi n and 1.0 v max for lvpecl. updated phase noise specs for 1 k/ 10 k/100 k/1 m/10 m/20 mhz offset to -120/-130/-135/-15 0/-150/-150dbc/hz, respectively, in the ac electrical specs table. added ?frequency range up to 1 ghz? condition to t odc spec. changed t od in the ac electrical specs table from 3 ns max to 5 ns max. added acronyms and ordering code definition. [+] feedback
cy2dl1504 document number: 001-56312 rev. *f page 13 of 14 *c 3090644 cxq 11/19/2010 changed v in and v out specs from 4.0v to ?lesser of 4.0 or v dd + 0.4? removed 200ma min lu spec, replaced with ?meets or exceeds jedec spec jesd78b ic latchup test? added ?v out = 0.75v - 1.75v? to i oz comments. moved v pp from ac spec table to dc spec table, removed v pp. removed r p spec for differential input clock pins in x and in x #. changed c in condition to ?measured at 10 mhz?. changed pn add specs for 10khz, 10mhz, and 20mhz offsets. added ?measured at 1 ghz? to t r , t f spec condition. removed specs t s, t h, t od, and t oe from ac spec table. removed v pp reference from figure 4. *d 3135189 cxq 01/12/2011 removed ?p reliminary? status heading. removed ?functional equivalent? bullet on page 1. added ?(see i oz )? note to pin 8 description in pin definitions . fixed typo and removed resistors from in x /in x # in logic block diagram . added figure 10 to describe t soe and t sod . *e 3090938 cxq 02/25/11 post to external web. *f 3208968 cxq 03/29/2011 changed r p max from 140 k to 165 k and updated r p in logic block diagram . document title: cy2dl1504 1:4 differential lvds fanout buffer with selectable clock input document number: 001-56312 revision ecn orig. of change submission date description of change [+] feedback
document number: 001-56312 rev. *f revised march 29, 2011 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2dl1504 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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